Design and Implementation of Binary Signed Vedic Multiplier for Real Time Digital Signal Processing Applications

In any digital signal processors (DSP’s) the speed of the multipliers plays a very important role. The precision of the multipliers also plays very important role along with its speed. For many high performance systems such as Digital Signal Processors, Microprocessors etc Multipliers are the key components. Since the Floating point multipliers can provide required precision but they are relatively slow and tend to consume more silicon area compared to fixed point (Q-format) multipliers. Since the Multipliers are the slowest component in any system, the system’s performance is determined by multiplier’s performance. In this paper we propose a fast fixed point signed multiplication using Urdhava Tiryakbhyam method of Vedic Mathematics.